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[VHDL-FPGA-Verilog] 123

Description: 基于FPGA的简单计算器系统的设计，使用了vhdl与verilog语言，附有文档介绍-Simple calculator system based on FPGA design using vhdl verilog language, with document describes
Platform: | Size: 5670912 | Author: 于智同 | Hits:

[VHDL-FPGA-Verilog] jianyijisuanqi

Description: 用VHDL实现简易计算器，实现加法、减法、乘法、除法的功能。-Use VHDL to realize simple calculator, can realize the function of addition, subtraction, multiplication, and division.
Platform: | Size: 16384 | Author: 双 | Hits:

[VHDL-FPGA-Verilog] calc_16_01_14

Description: A VHDL code for a simple calculator.It reads the operator and operands form the memory and execute
Platform: | Size: 589824 | Author: Prasad.M | Hits:

[VHDL-FPGA-Verilog] FPGADE270CACULATOR

Description: 本文介绍了一个简单的计算器的设计，该设计采用了现场可编程逻辑器件FPGA设计，并基于VHDL语言实现加减乘除功能，并用十进制显示在LCD1602上。-This article describes a simple calculator design that uses a field programmable logic device FPGA design and VHDL language based on arithmetic functions, and decimal display on LCD1602.
Platform: | Size: 3398656 | Author: 南宫崔浩 | Hits:

[VHDL-FPGA-Verilog] 7-timer

Description: 本代码是实现计算器的功能，用的是VHDL语言编写，全部实现过程都在这里面。-This code is to achieve the functions of the calculator, using the VHDL language, to achieve full process on the inside
Platform: | Size: 847872 | Author: 张天健 | Hits:

[VHDL-FPGA-Verilog] xuliejiancejisuanqikongzhiqi

Description: VHDL序列检测器，计算器，控制器编码以及实现方法。-VHDL sequential detector, calculator, controller and its implementation method.
Platform: | Size: 51200 | Author: 景生 | Hits:

[Other] calculate

Description: 基于VHDL，通过拨码开关实现数字输入，通过6位数码管实现输出。实现计算器的简单加、减、乘、除的基本功能-Based on VHDL, by DIP switch digital inputs, 6 digital control to achieve through output. Achieve a simple calculator to add, subtract, multiply, in addition to the basic functions
Platform: | Size: 271360 | Author: 高莹 | Hits:

[VHDL-FPGA-Verilog] AnJian_1602

Description: 计算器设计。采用了现场可编程逻辑器件FPGA设计，并基于VHDL语言实现加减乘除功能，并用十进制显示在数码管上。计算部分为加法器、减法器、乘法器和除法器组成。使用Altera公司的QuartusII开发软件进行功能仿真并给出仿真波形，并下载到试验箱,用实验箱上的按键开关模拟输入，用数码管显示十进制计算结果。通过外部按键可以完成四位二进制数的加、减、乘、除四种运算功能，其结果简单，易于实现。-Calculator design. Using a field programmable logic device FPGA design, VHDL language based on arithmetic function, and decimal display on the digital tube. Computing part adder, subtraction, multiplier and divider composition. QuartusII using Altera s development software for functional simulation and gives the simulation waveforms, and download to the chamber, with the key switch on the analog input experimental box with digital display decimal calculations. External keys can be done by four binary numbers to add, subtract, multiply, and divide four kinds of computing functions, the result is simple and easy to implement.
Platform: | Size: 13138944 | Author: 陈勒 | Hits:

[Software Engineering] jisuanqi

Description: VHDL语言编写的计算其程序，可实现简单的加减乘除运算。-Functions to achieve universal calculator
Platform: | Size: 2048 | Author: 李晨宇 | Hits:
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